Memory Architecture

Memory architecture significantly impacts communications in complex multi-processors with system-on-chip designs. Memory architecture determines the traffic flow of storage data in computer designs, which then defines the communications architecture.

Can memory and communications architecture have it all?

All of the methods for computer storage and information retrieval attempt to balance multi-dimensional constraints, such as reliability, power/speed, durability, memory space and cost. Depending on the specifics of applications, one or more of these requirements are typically compromised when another is improved. For example, flash memory is meant to accommodate many years of data storage; however, the flow of data traffic is very slow and, with frequent use, the storage cells of static memory deteriorate.

High speed data storage may cause a heat rush

Similarly, dynamic memory boasts fast access speeds for primary data storage as its key features; nevertheless, if this memory is not refreshed repeatedly with power surges that emit millions of high-temperature electrical currents per second, then all stored data decays and dissipates. Further, a large number of expensive business data-storage systems utilize data-bus storage designs for parallel or serial data access. Memory systems carry information, detect parity errors and may even correct errors, but reliability and cost are often prohibitive.

The never-ending race to keep up with technology

While the number of communications components is constantly increasing and expanding in today’s fast-paced computer storage world, allowing phenomenal inter-component communication systems, memory architecture engineers strive to produce multi-dimensional system designs that provide the best balance between the different performance constraints.

Advances to replace traditional approaches

Seeing the need to co-synthesize memory and communications architectures, designers still strive to build the fastest, most durable, most reliable and least expensive storage systems, all in one package, without sacrificing either constraint. One such design, Co-Synthesis for Memory and Communications Architectures, or COSMECA, is an automated, application-specific framework.

Testing of new memory and communication architectures in networking domains is showing great promise for optimal performance while slashing costs of memory space by more than 25 percent and decreasing the number of buses by at least 40 percent.