MPSoC Designs

Multiprocessor systems on chip (MPSoc) designs are extremely common in embedded systems that run everything from consumer products to industrial systems. As the name suggests, such systems contain multiple processors connected by an underlying communications architecture. The challenges posed by Moore's Law and increasing system complexity have forced MPSoC engineers to develop new strategies for managing all the data that flows between the chips and the shared memory space used by the system.

Shared bus designs

The bog standard MPSoC uses a shared bus system to shuttle data around the system. The problem with this approach is that each bus can only transmit so much data at a time. The amount of data a bus can transmit in a given time frame is known as its bandwidth. In complex MPSoCs, bus congestion is a serious problem that can slow down application performance. This could pose serious problems, especially in real time systems.

Bus matrices

To alleviate the bandwidth issue, modern MPSoCs often employ what is known as a bus matrix. This architecture optimizes data flow by adding redundancy to the system. This architecture also provides better performance when there is a large amount of variance in the data flow requirements during usage. One difficulty with this approach is that buses are extremely expensive. An overly generous matrix design could waste a ton of money, while a matrix that is too constraining cannot perform to standards. There are automated programs that attempt to determine the best matrix configuration for each application.

Network topology design

Designing applications for a MPSoC is a headache. Managing synchronization of multiple processing threads and the chip's memory space directly is quite the burden. One proposed solution to this problem is an abstraction layer similar to the TCP/IP stack. The programmer deals only with the top layers of the stack, while the machine deals with the rest. Some chip designers are even trying to implement an actual network communication infrastructure on the chip to replace the traditional bus architecture.

The march of technology is relentless. With modern MPSoCs sporting billions of transistors operating at multi-gigahertz clock speeds, engineers have no time to rest. Those design strategies that push the limits of processing power while keeping costs low are the ones that can see humanity off into the future.